1. Field of the Invention
The present invention relates to decision a timing synchronous circuit and a receiver circuit, and more particularly, to a decision timing synchronous circuit and a receiver circuit which extract the optimum decision timing in generating a demodulated signal from a signal that is oversampled at a frequency higher than the modulation rate of a received signal.
2. Description of the Related Art
For example, Bluetooth (registered trademark) receivers in a Bluetooth system or a wireless communication system employ 2.4 GHz band radio signals. Such a Bluetooth receiver includes a RFIC (Radio Frequency Integrated Circuit) transceiver for extracting a baseband signal at a 1 MHz symbol transmission rate from the aforementioned 2.4 GHz band radio signals, and a baseband receiver circuit for assembling a packet from the extracted baseband signal (digital serial signal).
Transmission of the baseband signal is initiated at a time slot boundary at every 625 μs, allowing first a 4-bit-length preamble, then a 64-bit-length synchronization word, and finally a variable-length payload to be transmitted.
The baseband receiver circuit in a Bluetooth receiver performs oversampling at a frequency higher than the modulation rate of the received signal to extract the received signal at intervals of the number of times of sampling corresponding to the modulation rate of the received signal for comparison with a predefined preamble pattern. After it is determined that the comparison result (correlation value) is equal to or greater than a desired expectation value, a location at which the maximum correlation value is obtained exceeding a threshold value is recognized as the optimum decision timing for demodulation.
The conventional baseband receiver circuit reproduces a clock signal simply by detecting only the rising edge and/or the falling edge of a received baseband signal, allowing the clock signal to be used for sampling the baseband signal to reconstruct symbols.
However, the aforementioned decision timing recognition method that employs the conventional baseband receiver circuit has the following problems.
For example, assuming that “b” is the number of symbols of a preamble and “n” is the number of times of oversampling per one symbol, the conventional decision timing synchronous circuit requires (b−1)×(n+1) or more shift register stages. Accordingly, this leads to a tremendous increase in the scale of the circuit for determining decision timing.
Additionally, as described above, decision timing is conventionally recognized based on the maximum correlation value between a signal obtained by oversampling at a frequency higher than the modulation rate and the preamble pattern. However, when a received signal is provided in an environment without so much noise, a plurality of maximal correlation values appearing successively may make it uncertain where the optimum timing is available, thus causing it difficult to recognize the optimum decision timing simply with the correlation value.
Furthermore, an offset can occur in the output from a signal detector though it depends on the mechanism of demodulation of the receiver circuit. For example, the FSK (Frequency Shift Keying) can be employed possibly with a frequency offset, while the BPSK (Binary Phase Shift Keying) can be employed possibly with a DC offset. Conventionally, before a decision timing synchronization is accomplished to obtain proper decision timing, it was necessary to compensate for and thereby cancel an offset, e.g., by AFC (Automatic Frequency Control) or the like.